1. Field of the Invention
The present invention relates to a phase-locked loop, and more particularly to an improved phase-locked loop used as a local oscillator in a radio communication system, which is capable of maintaining the control voltage of the voltage controlled oscillator (VCO) constant during the open-loop operation, while coping with the tendency of reducing a source voltage.
2. Description of Related Art
Phase-locked loops (PLL) are used as local oscillators in various communication systems. For example, a PLL is incorporated in a front-end transceiver of a radio communication system to synchronize a local oscillation signal with an externally supplied reference signal.
FIG. 1A illustrates a conventional PLL 100 used as a local oscillator in a radio communication system. PLL 100 comprises a phase detector 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator (VCO) 140, and a programmable divider 150, in which an output from the VCO 140 is fed back to the phase detector 110 to define a closed loop. The phase detector 110 compares the phase of the feedback clock supplied from the VCO 140 with a reference clock externally supplied, and outputs a signal in proportion to the phase difference. The charge pump 120 and the loop filter 130 extract a low-frequency component (i.e., a differential component) from the output signal of the phase detector 110, and supply the extracted low-frequency component to the VCO 140. The VCO 140 varies its oscillating frequency based on the output from the loop filter 130.
In general, the PLL used in a radio communication system has an FSK (frequency shift keying) modulating function, in addition to the above-described local oscillating function. FSK modulation is a function for shifting the output frequency between two or more prescribed values in accordance with, for example, multiple channels. In this case, the output frequency is locked to a carrier frequency under the closed loop, and then, the loop of the PLL 100 is opened. Under the open loop, a modulation signal is applied directly to the voltage controlled oscillator (VCO 140) from an external circuit (such as a baseband processing circuit connected to the front-end transceiver) to generate frequency-shifted waves.
In this manner, a PLL ordinarily operates in the closed-loop mode, functioning as a feedback circuit; however, it works in the open-loop mode when carrying out, for example, FSK modulation. The simplest way for opening the loop of the PLL 100 is turning off the charge pump 120.
FIG. 1B illustrates a conventional charge pump 120 used in the PLL 100. The charge pump 120 can be realized as a simple structure shown in FIG. 1B through a CMOS process. The charge pump 120 comprises a switch (PMOS transistor M3) 123 that is turned on by application of an up signal, and a switch (NMOS transistor M4) 124 that is turned on by application of a down signal.
In operation of the conventional charge pump 120 under the closed loop, a feedback signal input to the terminal fp of the phase detector 110 is compared with a reference signal input to the terminal fr. If the phase of the reference signal is ahead of that of the feedback signal, the phase detector 110 outputs a zero voltage or a negative voltage (which is referred to as xe2x80x9cLOWxe2x80x9d) from its output terminal pu, which causes the PMOS transistor (M3) 123 of the charge pump 120 to be turned on. Upon turning on the PMOS transistor (M3) 123, charge is accumulated in the capacitor of the loop filter 130. Assuming that the control characteristic of the VCO 140 (FIG. 1A) has a positive polarity, the control voltage of the VCO 140 increases in accordance with the accumulation of charge in the loop filter 130. Since the output frequency of the VCO 140 increases, the phase of the feed back signal becomes into consistent with that of the reference signal. On the other hand, if the phase of the reference signal input to the terminal fr is behind the feedback signal, LOW is output from the terminal pd to turn on the NMOS transistor (M4) 124 of the charge pump 120. Then, the charge is taken out of the loop filter 130, and the control voltage of the VCO 140 lowers. As a result, the output frequency of the VCO 140 decreases, and the phase of the feedback signal becomes into consistent with that of the reference signal.
Next, to open the loop of the PLL 100 for FSK modulation or other operations, the charge pump 120 is turned off. Both PMOS transistor 123 and NMOS transistor 124 of the charge pump 120 are turned off forcibly by an external control signal, regardless of the output of the phase detector 110. In the off state of the transistors 123 and 124, charge does not flow in and out of the capacitor of the loop filter 130. Consequently, the control voltage of the VCO 140 is maintained constant, and the output frequency of the VCO 140 becomes constant.
In this state, a modulation signal is applied directly to the input terminal vc of the VCO 140 from an adder of the external circuit (e.g., the baseband processing circuit). The output frequency of the VCO 140 changes in response to the change in the voltage level of the VCO 140, and a prescribed value of FSK modulation waves can be obtained.
In actual use of the charge pump 120 shown in FIG. 1B, the current becomes unbalanced. To overcome this problem, a current supply is used, or alternatively, the switches are differentiated to increase the speed of response of the charge pump 120.
By the way, as time goes by, the design rule of the CMOS process becomes finer and finer, and the power source voltage is lowered along with the continued miniaturization of the circuit design. An attempt is also made to reduce the threshold value of a transistor for the purpose of increasing the operation speed of a logic circuit. However, if the threshold voltage is set lower, off-leakage of the MOS transistor becomes large. For example, when PMOS transistor 123 and NMOS transistor 124 are turned off in the charge pump 120 shown in FIG. 1B to open the loop, the charge accumulated in the capacity of the loop filter 130 fluctuates due to off-leakage of the transistors 123 and 124, and consequently, the control voltage of the VCO 140 abruptly varies.
FIG. 2 illustrates a simulation result of the voltage drift of the loop filter due to off-leakage that occurs when PMOS transistor 123 and NMOS transistor 124 are turned off in the conventional charge pump 120 of the PLL 100. As time passes, the amount of voltage change increases, and the voltage varies by 0.15V or more in 100 xcexcs. This phenomenon prevents the PLL 100 from maintaining the transmission frequency constant under the open loop, and FSK modulation can not be carried out appropriately.
To overcome this problem, transistors with a relatively long channel-length may be used to reduce the off-leakage from PMOS transistor (M3) and NMOS transistor (M4). However, the size of the transistors M3 and M4 that are connected to the output of the charge pump 120 becomes large, and another problem arises, that is, the speed of response of the charge pump 120 slows down.
The present invention was conceived to overcome the above-described problems in the prior art, and it is an object of the invention to provide a phase-locked loop that can maintain the control voltage of the voltage control oscillator (VCO) constant under the open loop, while coping with the trend of reducing the power source voltage along with the miniaturization of the CMOS process.
To achieve the object, a third switch is inserted before the output of the charge pump to control switching between the open loop and the closed loop of the PLL. The third switch can be realized as, for example, a MOS transistor.
To be more precise, a phase-locked loop (PLL) comprises a phase detector receiving an externally supplied reference clock and a feedback clock; a charge pump connected to the output of the phase detector; a loop filter extracting a low-frequency component from the output of the charge pump; and a voltage controlled oscillator (VCO) having an input connected to the output of the loop filter and an output connected to the feedback clock supplied to the phase detector, in which the charge pump comprises a first switch that controls outputting a negative current based on the output of the phase detector, a second switch that controls outputting a positive current based on the output of the phase detector, a third switch connected between the first switch and the second switch to control an output to the loop filter, and an input terminal receiving a switching control signal for controlling opening and closing of the third switch.
With this arrangement, a long-channel transistor with little leakage current can be used as the third switch, while using high-speed short-channel transistors for the first and second switches. Consequently, the leakage current flowing during the open-loop operation can be reduced, without deteriorating the speed of response, and the control voltage of the voltage controlled oscillator (VCO) can be maintained constant. In addition, by inserting the third switch (i.e., the resistance) before the output of the charge pump, fluctuation of electric current flowing into and out of the loop filter during the open-loop operation can be reduced. This also results in a constant control voltage of the voltage controlled oscillator (VCO).
In an embodiment, the input terminal receiving the switching control signal is connected directly to the third switch to control the opening and closing of the loop, regardless with the ON/OFF states of the first and second switches. This arrangement can reduce undesirable off-leakage, without slowing down the speed of response.
In another embodiment, the charge pump further comprises a control circuit connected before the first and second switches to control the ON/OFF operations of the first, second, and third switches. In this case, the input terminal for receiving the switching control signal is connected to the control circuit. To open the loop of the PLL, the control circuit controls the first, second, and third switches so that the third switch is turned off, while turning on the first and second switches.
With this arrangement, a substantially equal amount of electric current flows through the first switch and the second switch during the open-loop operation, and the electric potential between the first switch and the second switch stays at or near equal to one-half of the control voltage of the voltage controlled oscillator (VCO). Consequently, the off-leak current can be further reduced in the open loop.